1. Technical Field
The present invention relates to a memory module and to an auxiliary module for memory.
2. Related Art
Memory modules composed of multiple semiconductor memory chips that have been mounted and interconnected on a circuit board, and provided with connector terminals for connection to a computer, have enjoyed widespread use for some time. SDRAM (Synchronous Dynamic Random Access Memory) is one type of memory with which these kinds of memory modules may be equipped. An SDRAM is internally divided into several banks, with each bank being operable independently. In SDRAM, memory cells targeted for access are identified by a bank address, a row address, and a column address which have been output by a memory controller provided to the computer. The bank address is input to the SDRAM using a bank address signal line, while the row address and the column address are input to the SDRAM using a shared signal line. The row address and the column address are input to the SDRAM over two cycles, in the order of row address followed by column address.
The numbers of memory cells in memory modules have seen an increase in association with the larger memory capacities, which in turn will cause a change in the number of bits of the bank address, the number of bits of the row address, and the number of bits of the column address which are used for identifying memory cells targeted for access. For example, if the number of banks is doubled, there will be a one-bit increase in the number of bits in the bank address. A resultant drawback is that where a memory module equipped with large capacity memory is connected to a computer whose memory controller is not compatible with such a memory module, i.e. where the numbers of bits of the addresses output by the memory controller do not match the numbers of bits of the addresses for identifying memory cells targeted for access, the computer (the memory controller) will only be able to access a portion of the memory cells in the memory module.
Accordingly, there have been proposed a number of technologies for use in memory modules, intended to enable access to all memory cells of the memory module even in instances where the numbers of bits of the addresses that are output by the memory controller do not respectively match the numbers of bits of the addresses for identifying memory cells targeted for access.
However, even according to the technologies taught in the aforementioned technologies, there were instances where memory module failed to operate normally.
An advantage of some aspects of the invention is to enable access to all memory cells of a memory module and to carry out normal operation of the memory module, even in instances where the number of bits of the bank address, the number of bits of the row address, and the number of bits of the column address that are output by the memory controller do not respectively match the number of bits of the bank address, the number of bits of the row address, and the number of bits of the column address for identifying memory cells targeted for access.
The entire disclosure of Japanese patent application No. 2008-261521 of BUFFALO is hereby incorporated by reference into this document.